530 lines
36 KiB
Plaintext
530 lines
36 KiB
Plaintext
┌─────────────────────────────────────────────╖
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│ 2.Field ALU (data processing unit). ║
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╘═════════════════════════════════════════════╝
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The data processing unit (hereinafter ALU) of proposed systems
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is built with use of the following functioning junctions:
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1) 4 microprocessor sections KM1804BC1, which form the
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16-bit based ALU.
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2) Condition control and shift Scheme KM1804BP2, which is ÀσѼá π»αáó½Ñ¡¿∩ ß«ßΓ«∩¡¿Ñ¼ ¿ ßñó¿úἿ èÔ1804éÉ2, ¬«Γ«αá∩
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intended to joint work with processor element BC1 and
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provides closing of data around microprocessor section.
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Given microcircuit provides the functions of the
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register of the conditions and forming of the signal of
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the carrying, mix of the sources of the input carry
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signal ALU, organizes 32 types of shift (arithmetical,
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logical, round-robin), which can be usual or double-
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length, contains two 4-bit register of the condition,
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executes 16 operations on forming the signal of the
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condition.
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3) Microcircuit of the framing:
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4-bit registers of operands (RAA,RAB);
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The Multiplexers of select of the source operand, which
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allows to address the registers participating in operations
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ALU or from MIM, or on the address, keeping in RAA and RAB.
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To manage afore-mentioned device, each command in MIM contains
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the following fields.
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Includes:
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Microcircuit KM1804BC1:
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BC1_MI² - operation in BC1;
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A,B - number of ALU registers;
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OEY - acception for issues of result from ALU;
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Microcircuit KM1804BP2:
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BP2_MI² - operation in BP2;
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E.ZNCV - permit of per-bit marks writing in RM;
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OECT - permit an issue of the code term;
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CEM - permit writing the marks in RM;
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CEN - permit writing the marks in RN;
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SE - permit of the shift performing;
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Microcircuits of the framing:
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MSA - source of operand in ALU (MIM or RA);
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MSB - source of operand in ALU (MIM or RB);
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EWA - writing in operand registers RA;
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EWB - writing in operand registers RB.
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┌────────╖
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│ BC1_MI²║ THE MICROINSTRUCTION FIELD OF THE MICROCIRCUIT BC1.
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╘════════╝ ──────────────────────────────────────────────────┘
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Purpose.
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Assign the operation executed in ALU. Given field contains
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several sections (the flap), each defines the nature
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of executed operations.
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1) Field of the result receiver in ALU;
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2) Field of operation in ALU;
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3) Field of operation in ALU.
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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┌───────────╖
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│BC1_MI².876║ THE RECEIVER OF THE OPERATION RESULT IN ALU.
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╘═══════════╝ ───────────────────────────────────────────┘
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Purpose.
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Field of the result receiver in ALU (bits 8,7,6).
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Defines where fits result of the operations.
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┌───┬───────────────────────────────────────────────────┐
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│MI │ │
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│876│ where will get the result of operation processing │
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├───┼───────────────────────────────────────────────────┤
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│000│ F -> Q │
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│001│ result of operations in ALU does not place in │
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│ │ any internal registers and is used only for │
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│ │ indirect effect, for instance restore all │
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│ │ operation flags, or output the result of │
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│ │ operation on the data bus. │ │
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│010│ F -> B and result does not output on bus, │
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│ │ but value of the register - an operand A │
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│011│ F -> B │
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│100│ F/2 -> B, Q/2 -> Q │
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│101│ F/2 -> B │
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│110│ 2F -> B, 2Q -> Q │
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│111│ 2F -> B │
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└───┴───────────────────────────────────────────────────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 001 became assigned.
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┌───────────╖
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│BC1_MI².543║ OPERATIONS IN ALU.
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╘═══════════╝ ─────────────────┘
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Purpose.
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The field of operations in ALU (bits 5,4,3). Defines
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nature of the transformation on chosen operand.
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┌───┬──────┬───────────────┐
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│MI │mnemo-│ operation │
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│543│ nics │ in ALU │
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├───┼──────┼───────────────┤
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│000│ ADD │ R+S+CI │
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│001│ SUB │ S-R-1+CI │
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│010│ SUB │ R-S-1+CI │
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│011│ OR │ R or S │
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│100│ AND │ R and S │
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│101│ NAND │ not(R) and S│
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│110│ XOR │ R xor S │
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│111│ NXOR │ not(R xor S)│
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└───┴──────┴───────────────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 000 became assigned.
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┌───────────╖
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│BC1_MI².210║ FIELD OF THE OPERATION OPERANDS IN ALU.
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╘═══════════╝ ──────────────────────────────────────┘
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Purpose.
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The field of operations in ALU (bits 2,1,0). Defines
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operands, which participate in operations performing.
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┌───┬───────────┬──────┐
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│MI │ │ │
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│210│ mnemonics │R S│
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├───┼───────────┼──────┤
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│000│ Rx , RQ ; │A Q│
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│001│ Rx , Rx ; │A B│
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│010│ Z , RQ ; │Z Q│
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│011│ Z , Rx ; │Z B│
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│100│ Z , Rx ; │Z A│
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│101│ Val, Rx ; │D A│
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│110│ Val, RQ ; │D Q│
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│111│ Val, Z ; │D Z│
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└───┴───────────┴──────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 000 became assigned.
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┌────────╖
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│ A, B ║ NUMBERS OF REGISTERS IN ALU, WHICH ARE USED IN OPERATION.
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╘════════╝ ────────────────────────────────────────────────────────┘
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Purpose.
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Fields define numbers of registers in ALU, which are
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used in performing an operation. Values from this field
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are accordingly output on entrances A and B of the chip
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BC1. The switching condition of these flap to microcircuit
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BC1 are signals on the operands source select multiplexors
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MSA=0 and MSB=0.
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The note.
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Values are entered in hexadecimal code.
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When entered a new command then assigned zero GPRs
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(general-purpose registers).
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┌────────╖
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│ OEY ║ PERMIT FOR THE RESULT OUTPUT.
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╘════════╝ ────────────────────────────┘
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Purpose.
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Permit for output of the result from ALU (BC1) on
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system data bus.
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Level : 0 - Active (output permit)
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1 - Passive (output prohibited).
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The note.
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Values are entered in binary code.
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While entering a new command the outputing of the
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operations result in ALU is prohibited.
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┌─────────╖
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│ BP2_MI² ║ FIELD OF THE MICROINSTRUCTION IN THE BP2 CHIP.
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╘═════════╝ ─────────────────────────────────────────────┘
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Purpose.
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It will assign microinstruction which is executed in
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device of condition and shift management KM1804BP2,
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which provides a data closing around microprocessor
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section (KM1804BC1). This field contains several
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sections:
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1) The management field of the signal carrying CI;
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2) The control field of the shift performing;
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3) Field which controls the output of the code
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condition and loading of the register marks.
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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┌──────────╖
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│BP2_MI².CB║ THE MANAGEMENT OF CI SIGNAL.
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╘══════════╝ ───────────────────────────┘
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Purpose.
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Field that controls signal of carrying CI (bits 12,11).
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Values of this field allows to commute the different
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signals on entry Si of ALU sections.
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┌──┬──────┬───────────────────────────────────────────────────────┐
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│MI│mnemo-│ │
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│CB│ nics │ shift, that entered in ALU entry │
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├──┼──────┼───────────────────────────────────────────────────────┤
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│00│ Z │ 0 │
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│01│not Z │ 1 │
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│10│ │ is not used │
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│11│ RM_C │signal of carrying is assigned as output of À registers│
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│ │ RN_C │on the marks RM and RN in the following order: │
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│ │not │under MI.5 = 1 with RM.C, otherwise with RN.C; │
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│ │ RM_C│under MI.321 = 100 signals transforms by inversion │
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│ │ RN_C│under any other combinations - without it │
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└──┴──────┴───────────────────────────────────────────────────────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 00 became assigned.
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┌───────────╖
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│BP2_MI².A-6║ FIELD OF SHIFT CONTROL.
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╘═══════════╝ ──────────────────────┘
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Purpose.
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Field that controlling the shift performing (bits 10-6).
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┌─────┬────┬───────────────┬───────────────────────────────────────────┐
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│ │ │ │ forming the shift signals for the ALU │
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│ MI │ │ │ registers (with signal SE = 0 ) │
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│A9876│dec.│ mnemonics ├──────────────┬──────────┬─────────────────┤
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│ │ │ │ on register │ on reg. │ load of C flag │
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│ │ │ │ receiv. resu.│ RQ │ in reg. mark RM │
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├─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┤
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│ R I G H T S H I F T S │
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├─────┬────┬───────────────┬──────────────┬──────────┬─────────────────┤
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│00000│ 00 │ SR.0 │SRB:=0 │SRQ:=0 │ no │
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│00001│ 01 │ SR.1 │SRB:=1 │SRQ:=1 │ no │
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│00010│ 02 │ SRL (SR.2) │SRB:=0 │SRQ:=RM.N │ RM.C:=SRB │
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│00011│ 03 │ SR.3 │SRB:=1 │SRQ:=SRB │ no │
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│00100│ 04 │ SR.4 │SRB:=RM.C │SRQ:=SRB │ no │
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│00101│ 05 │ SR.5 │SRB:=RM.N │SRQ:=SRB │ no │
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│00110│ 06 │ SR.6 │SRB:=0 │SRQ:=SRB │ no │
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│00111│ 07 │ SRWL (SR.7) │SRB:=0 │SRQ:=SRB │ RM.C:=SRQ │
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│01000│ 08 │ SR.8 │SRB:=SRB │SRQ:=SRQ │ RM.C:=SRB │
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│01001│ 09 │ SR.9 │SRB:=RM.C │SRQ:=SRQ │ RM.C:=SRB │
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│01010│ 10 │ SR.10 │SRB:=SRB │SRQ:=SRQ │ no │
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│01011│ 11 │ SR.11 │SRB:=CO │SRQ:=SRB │ no │
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│01100│ 12 │ SR.12 │SRB:=RM.C │SRQ:=SRB │ RM.C:=SRQ │
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│01101│ 13 │ SR.13 │SRB:=SRQ │SRQ:=SRB │ RM.C:=SRQ │
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│01110│ 14 │SRA SRWA(SR.14)│SRB:=NO xor VO│SRQ:=SRB │ no │
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│01111│ 15 │ SR.15 │SRB:=SRQ │SRQ:=SRB │ no │
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├─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┤
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│ L E F T S H I F T S │
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├─────┬────┬───────────────┬──────────────┬──────────┬─────────────────┤
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│10000│ 16 │ SLL (SL.16) │SLB:=0 │SLQ:=0 │ RM.C:=SLB │
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│10001│ 17 │ SL.17 │SLB:=1 │SLQ:=1 │ RM.C:=SLB │
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│10010│ 18 │ SLA (SL.18) │SLB:=0 │SLQ:=0 │ no │
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│10011│ 19 │ SL.19 │SLB:=1 │SLQ:=1 │ no │
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│10100│ 20 │ SLWL (SL.20) │SLB:=SLQ │SLQ:=0 │ RM.C:=SLB │
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│10101│ 21 │ SL.21 │SLB:=SLQ │SLQ:=1 │ RM.C:=SLB │
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│10110│ 22 │ SLWA (SL.22) │SLB:=SLQ │SLQ:=0 │ no │
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│10111│ 23 │ SL.23 │SLB:=SLQ │SLQ:=1 │ no │
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│11000│ 24 │ SL.24 │SLB:=SLB │SLQ:=SLQ │ RM.C:=SLB │
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│ │ │ │ │ │ │
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│11001│ 25 │ SL.25 │SLB:=RM.C │SLQ:=SLB │ RM.C:=SLB │
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│11010│ 26 │ SL.26 │SLB:=SLB │SLQ:=SLB │ no │
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│11011│ 27 │ SL.27 │SLB:=RM.C │SLQ:=0 │ no │
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│11100│ 28 │ SL.28 │SLB:=SLQ │SLQ:=RM.C │ RM.C:=SLB │
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│11101│ 29 │ SL.29 │SLB:=SLQ │SLQ:=SLB │ RM.C:=SLB │
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│11110│ 30 │ SL.30 │SLB:=SLQ │SLQ:=RM.C │ no │
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│11111│ 31 │ SL.31 │SLB:=SLQ │SLQ:=SLB │ no │
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└─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 00000 became assigned.
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┌───────────╖
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│BP2_MI².5-0║ CONDITION CT OR LOADING REGISTER OF MARKS.
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╘═══════════╝ ─────────────────────────────────────────┘
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Purpose.
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The field that controls the leaving of condition code and
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boot of register marks (bits 5-0).The contents of the given
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field can be interpretated in a different type:
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1) forming the signal of the logical condition
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(at signal OECT=0);
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2) operations of the loading register marks.
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(at signal OECT=1);
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┌──────┬───┬──────┬────────────────────────────────────────┐
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│ MI │ │mnemo-│ forming signal of a logical condition │
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│543210│dec│ nics │ (at signal OECT = 0 ) │
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│──────┼───┼──────┼────────────────────────────────────────┤
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│000000│ 00│ │CT:=RN.Z or (RN.N xor RN.V); │
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│000001│ 01│ │CT:=not(RN.N xor RN.V) and not(RN.Z); │
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│000010│ 02│ │CT:=RN.N xor RN.V; │
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│000011│ 03│ │CT:=not(RN.N xor RN.V); │
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│000100│ 04│ RN_Z │CT:=RN.Z; │
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│000101│ 05│ │CT:=not(RN.Z); │
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│000110│ 06│ RN_V │CT:=RN.V; │
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│000111│ 07│ │CT:=not(RN.V); │
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│001000│ 08│ │CT:=RN.C or RN.Z; │
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│001001│ 09│ │CT:=not(RN.C) and not(RN.Z); │
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│001010│ 10│ RN_C │CT:=RN.C; │
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│001011│ 11│ │CT:=not(RN.C); │
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│001100│ 12│ │CT:=not(RN.C) or RN.Z; │
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│001101│ 13│ │CT:=RN.C and not(RN.Z); │
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│001110│ 14│ │CT:=NO xor RM.N; │
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│001111│ 15│ │CT:=not(NO xor RM.N); │
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│010000│ 16│ │CT:=RgN.Z or (RN.N xor RN.V); │
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│010001│ 17│ │CT:=not(RN.N xor RN.V) and not(RN.Z); │
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│010010│ 18│ │CT:=RN.N xor RN.V; │
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│010011│ 19│ │CT:=not(RN.N xor RN.V); │
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│010100│ 20│ │CT:=RN.Z; │
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│010101│ 21│ │CT:=not(RN.Z); │
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│010110│ 22│ │CT:=RN.V; │
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│010111│ 23│ │CT:=not(RN.V); │
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│011000│ 24│ │CT:=RN.C or RN.Z; │
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│011001│ 25│ │CT:=not(RN.C) and not(RN.Z); │
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│011010│ 26│ │CT:=RN.C; │
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│011011│ 27│ │CT:=not(RN.C); │
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│011100│ 28│ │CT:=not(RN.C) or RN.Z; │
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│011101│ 29│ │CT:=RN.C and not(RN.Z); │
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│011110│ 30│ RN_N │CT:=RN.N; │
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│011111│ 31│ │CT:=not(NO xor RM.N); │
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│100000│ 32│ │CT:=RM.Z or (RM.N xor RM.V); │
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│100001│ 33│ │CT:=not(RM.N xor RM.V) and not(RM.Z); │
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│100010│ 34│ │CT:=RM.N xor RM.V; │
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│100011│ 35│ │CT:=not(RM.N xor RM.V); │
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│100100│ 36│ RM_Z │CT:=RM.Z; │
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│100101│ 37│ │CT:=not(RM.Z); │
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│100110│ 38│ RM_V │CT:=RM.V; │
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│100111│ 39│ │CT:=not(RM.V); │
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│101000│ 40│ │CT:=RM.C or RM.Z; │
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│101001│ 41│ │CT:=not(RM.C) and not(RM.Z); │
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│101010│ 42│ RM_C │CT:=RM.C; │
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│101011│ 43│ │CT:=not(RM.C); │
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│101100│ 44│ │CT:=not(RM.C) or RM.Z; │
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│101101│ 45│ │CT:=RM.C and not(RM.Z); │
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│101110│ 46│ RM_N │CT:=RM.N; │
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│101111│ 47│ │CT:=not(RM.N); │
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│110000│ 48│ │CT:=ZO or (NO xor VO); │
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│110001│ 49│ │CT:=not(NO xor VO) and not(ZO); │
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│110010│ 40│ NXORV│CT:=NO xor VO; │
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│110011│ 51│ │CT:=not(NO xor VO); │
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│110100│ 52│ ZO │CT:=ZO; │
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│110101│ 53│ │CT:=not(ZO); │
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│110110│ 54│ VO │CT:=VO; │
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│110111│ 55│ │CT:=not(VO); │
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│111000│ 56│ │CT:=CO or ZO; │
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│111001│ 57│ ZORC │CT:=not(CO) and not(ZO); │
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│111010│ 58│ CO │CT:=CO; │
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│111011│ 59│ │CT:=not(CO); │
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│111100│ 60│ │CT:=not(CO) or ZO; │
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│111101│ 61│ │CT:=CO and not(ZO); │
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│111110│ 62│ NO │CT:=NO; │
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│111111│ 63│ │CT:=not(NO); │
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└──────┴───┴──────┴────────────────────────────────────────┘
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The note: if mnemonics is not given, than it is necessary to use command FIELD.
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 000000 became assigned.
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┌──────┬───┬─────────────────┬────────────────────────────────────────┐
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│ MI │ │ │operations for loading of register marks│
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│ │ │ ├───────────────────┬────────────────────┤
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│543210│dec│ mnemonics │ operation in RN │operation in RM when│
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│ │ │ │ (when CEN=0) │ CEM, E.C,Z,N,V=0 │
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├──────┼───┼─────────────────┼───────────────────┼────────────────────┤
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│000000│ 00│ LOAD RN,RM; │ RN:=RM; │ no loading │
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│000001│ 01│ LOAD RM,NZ; │ RN:=1111 │ RM:=1111 │
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│ │ │ LOAD RN,NZ; │ │ │
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│000010│ 02│ LOAD RM,RN; │ RN <--> RM │ RM:=RN │
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│000011│ 03│ LOAD RM,Z; │ RN:=0000 │ RM:=0000 │
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│ │ │ LOAD RN,Z; │ │ │
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│000100│ 04│ LOAD RN,FLAGS; │ RN:=FLAGS │ Z:=ZO N:=NO C<-->V │
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│000101│ 05│ │ RN:=FLAGS │ RM:=not RM │
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│000110│ 06│ LOAD RM,FLAGS; RN:=FLAGS except │ RM:=FLAGS │
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│000111│ 07│ LOAD @RN,FLAGS; RN.V:=RN.V xor VO │ RM:=FLAGS │
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│001000│ 08│ LOAD @RM,FLAGS; │ RN.Z:=0 RM:=FLAGS except │
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│001001│ 09│ │ RN.Z:=1 RM.C:=not CO │
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│001010│ 10│ │ RN.C:=0 │ RM:=FLAGS │
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│001011│ 11│ │ RN.C:=1 │ RM:=FLAGS │
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│001100│ 12│ │ RN.N:=0 │ RM:=FLAGS │
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│001101│ 13│ │ RN.N:=1 │ RM:=FLAGS │
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│001110│ 14│ │ RN.V:=0 │ RM:=FLAGS │
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│001111│ 15│ │ RN.V:=1 │ RM:=FLAGS │
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│010000│ 16│ │ RN:=FLAGS │ RM:=FLAGS │
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│010001│ 17│ │ RN:=FLAGS │ RM:=FLAGS │
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│010010│ 18│ │ RN:=FLAGS │ RM:=FLAGS │
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│010011│ 19│ │ RN:=FLAGS │ RM:=FLAGS │
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│010100│ 20│ │ RN:=FLAGS │ RM:=FLAGS │
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│010101│ 21│ │ RN:=FLAGS │ RM:=FLAGS │
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│010110│ 22│ │ RN:=FLAGS │ RM:=FLAGS │
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│010111│ 23│ │ RN:=FLAGS │ RM:=FLAGS │
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│011000│ 24│ RN:=FLAGS except RM:=FLAGS except │
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│011001│ 25│ RN.C:=not CO RM.C:=not CO │
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│011010│ 26│ │ RN:=FLAGS │ RM:=FLAGS │
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│011011│ 27│ │ RN:=FLAGS │ RM:=FLAGS │
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│011100│ 28│ │ RN:=FLAGS │ RM:=FLAGS │
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│011101│ 29│ │ RN:=FLAGS │ RM:=FLAGS │
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│011110│ 30│ │ RN:=FLAGS │ RM:=FLAGS │
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│011111│ 31│ │ RN:=FLAGS │ RM:=FLAGS │
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│100000│ 32│ │ RN:=FLAGS │ RM:=FLAGS │
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│100001│ 33│ │ RN:=FLAGS │ RM:=FLAGS │
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│100010│ 34│ │ RN:=FLAGS │ RM:=FLAGS │
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│100011│ 35│ │ RN:=FLAGS │ RM:=FLAGS │
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│100100│ 36│ │ RN:=FLAGS │ RM:=FLAGS │
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│100101│ 37│ │ RN:=FLAGS │ RM:=FLAGS │
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│100110│ 38│ │ RN:=FLAGS │ RM:=FLAGS │
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│100111│ 39│ │ RN:=FLAGS │ RM:=FLAGS │
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│101000│ 40│ RN:=FLAGS except RM:=FLAGS except │
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│101001│ 41│ RN.C:=not CO RM.C:=not CO │
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│101010│ 42│ │ RN:=FLAGS │ RM:=FLAGS │
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│101011│ 43│ │ RN:=FLAGS │ RM:=FLAGS │
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│101100│ 44│ │ RN:=FLAGS │ RM:=FLAGS │
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│101101│ 45│ │ RN:=FLAGS │ RM:=FLAGS │
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│101110│ 46│ │ RN:=FLAGS │ RM:=FLAGS │
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│101111│ 47│ │ RN:=FLAGS │ RM:=FLAGS │
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│110000│ 48│ │ RN:=FLAGS │ RM:=FLAGS │
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│110001│ 49│ │ RN:=FLAGS │ RM:=FLAGS │
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│110010│ 40│ │ RN:=FLAGS │ RM:=FLAGS │
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│110011│ 51│ │ RN:=FLAGS │ RM:=FLAGS │
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│110100│ 52│ │ RN:=FLAGS │ RM:=FLAGS │
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│110101│ 53│ │ RN:=FLAGS │ RM:=FLAGS │
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│110110│ 54│ │ RN:=FLAGS │ RM:=FLAGS │
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│110111│ 55│ │ RN:=FLAGS │ RM:=FLAGS │
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│111000│ 56│ RN:=FLAGS except RM:=FLAGS except │
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│111001│ 57│ RN.C:=not CO RM.C:=not CO │
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│111010│ 58│ │ RN:=FLAGS │ RM:=FLAGS │
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│111011│ 59│ │ RN:=FLAGS │ RM:=FLAGS │
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│111100│ 60│ │ RN:=FLAGS │ RM:=FLAGS │
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│111101│ 61│ │ RN:=FLAGS │ RM:=FLAGS │
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│111110│ 62│ │ RN:=FLAGS │ RM:=FLAGS │
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│111111│ 63│ │ RN:=FLAGS │ RM:=FLAGS │
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└──────┴───┴─────────────────┴───────────────────┴────────────────────┘
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The note: if mnemonics is not given, than it is necessary to use command FIELD;
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the torn lines in table mean that is given one command
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for two codes.
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²).
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When entered a new command the code 000000 became assigned.
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┌─────────╖
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│E.C,Z,N,V║ BITWISE PERMIT THE RECORDING IN REGISTER RM.
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╘═════════╝ ───────────────────────────────────────┘
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Purpose.
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The permit of writing of the marks in one bit of the
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marks register (RM) of BP2 chip. Record is provided
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when signal SEM=0
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Level : 0 - Active (writing is permited)
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1 - Passive (writing is prohibited).
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The note.
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Values are entered in binary code.
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When entering the new command then bitwise writing for all marks is resolved.
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┌─────────╖
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│ OECT ║ PERMIT THE ISSUE OF THE TERM CODE ON CT OUTPUT.
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╘═════════╝ ──────────────────────────────────────────────┘
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Purpose.
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Permit the issue of the term code on CT output of the
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KM1804BP2 chip. Herewith the formed signal on CT output
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is defined by code in field BP2_MI².5-0 (bits 5-0 of
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the microinstruction codes for the BP2 chip). The signal
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of the logical condition is formed when OECT=0.
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Level :
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0 - Active (forming permit)
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1 - Passive (forming prohibited).
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The note.
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Values are entered in binary code.
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When entering the new command the forming of logical
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conditions is prohibited.
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┌─────────╖
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│ CEN,CEM ║ PERMIT OF MARKS WRITING IN REGISTERS RN/RM.
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╘═════════╝ ──────────────────────────────────────────┘
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Purpose.
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|
Permit of marks writing in registers RN/RM
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of KM1804BP2 chip.
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Level : 0 - Active (writing permit)
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1 - Passive (writing prohibited).
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|
The note.
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Values are entered in binary code.
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When entering the new command record in registers prohibited..
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┌─────────╖
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│ SE ║ PERMIT OF THE SHIFT PERFORMING.
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|
╘═════════╝ ──────────────────────────────┘
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|
Purpose.
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|
The permit of the shift performing in KM1804BP2 chip.
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|
Level : 0 - Active (shift permit)
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1 - Passive (shift prohibited).
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|
The note.
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Values are entered in binary code.
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When entering the new command the shifts are prohibited.
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┌─────────╖
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│ MSA,MSB ║ CHOICE A SOURCES OF THE OPERAND ADDRESS.
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╘═════════╝ ───────────────────────────────────────┘
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Purpose.
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|
Choice of the source operand in ALU (MIM or RA). Field contains
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the signals of the multiplexer that controls a choice of the
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address source of operand for operation in ALU.
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Value : 0 - The number of the KM1804BC1 chip register is
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extracted from MIM;
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1 - The number of the KM1804BC1 chip register is
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|
extracted from external register.
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|
The note.
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|
Values are entered in binary code.
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|
When entering a new command the multiplexer chooses a number
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|
of the register from microinstructions memory.
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|
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┌─────────╖
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│ EWA,EWB║ WRITING INFORMATION IN OPERAND SELECT REGISTERS IN ALU.
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|
╘═════════╝ ─────────────────────────────────────────────────────────┘
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|
Purpose.
|
|
The low-level signal provides record of information from
|
|
system bus that is given in 4-bit registers (RA,RB)
|
|
of the operand choice in ALU. The number buses bits
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|
that is used for loading registers are defined when
|
|
adjusting the system.
|
|
Level : 0 - Active (write)
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|
1 - Passive (storage).
|
|
The note.
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|
Values are entered in binary code.
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|
When entering the new command the record in registers are prohibited.
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