6. Arithmetic-logical commands. ═══════════════════════════════ The arithmetic-logical commands serves for performing some microinstruction as adding, subtractions, bitwise logical operation, operation of the shifts, loading, inversion of separate register in Arithmetic-Logical Unit (ALU), that is built on four microcircuits BC1 and one m/c BP2. In a whole there is 7 commands, formats of which will are considered in given section: 1)ADD - arithmetical adding; 2)SUB - arithmetical subtraction; 3)OR - logical adding; 4)AND - logical multiplying; 5)XOR - logical subtraction (excluding "OR"); 6)NAND - logical multiplying in which first operand is taking with inversion; 7)NXOR - logical subtraction in which result is inverted; Next will be considered: 6.1. Assign of register shifts. 6.2. Assign of the result receiver. 6.3. Assign of operand, on which is executed some operation. 6.4. Assign of the input carrying. 6.1. Receiver of the result. ──────────────────────────── As receiver of the result can emerge the following operands: 1) RQ - work registers of ALB; 2) R0..R15 - one of the register of the general-purpose (RGP); 3) RB - RGP, number of which is determined in RB; 4) NIL - the empty receiver (the result is not saved, but can protrude on BD, as well as can be used flags, which are installed when the operations is perform). The assigning of the RB implies use of RGP, the number of which is kept in stood register RB. 6.2. Operands, on which operation is assigned. ──────────────────────────────────────────────── Any one of described above commands allows to execute the actions on two operands and place the result in to operations register, in general event not coinsiding with operand, on which operation was executed. For example, ADD RQ,R1,R2; But often receiver of the result is simultaneously and one of the worker operand. Then possible lower writing of this operand twice, and assembler by itself will be undertake the task hipping an operand commands. For example: SUB RQ,1; Here is possible operands, which possible indicate when command assign: 1) Z - "internal" zero, specially realization in BC1 chip is to protect data bus from frequent trivial information; 2) RQ - work register of ALB; 3) R0..R15 - one of the general-purpose register; 4) RA,RB - GPR, number of which is determined in RA or RB; 5) numeric constant; 6) BUS_D - writing of such operand speaks of that, that operand will be scanned from data bus. 6.3. Assign of shift register. ────────────────────────────── 6.3.1. Structured scheme of the shift performing on ALB. 6.3.2. Standard types of shifts. 6.3.3. General types of shifts. The arithmetic-logical block, on which is built ALU of microprocessor complex has as one of their own function possibility of simultaneously with execution one of the arithmetic-logical operation to produce the shift of the register-receiver. Control of shift type is realized by microinstruction, entering on entry MI(10-6) m/c BR2. Shift is assigned by microinstruction MI(8) m/c BH1. Herewith is possible to realize simultaneous shift of worke register RQ. For this purpose is necessary to place before operand of the shift the operator of the modification "@" which is indicates to assembler that is produced simultaneous shift of the register-receiver and work register RQ. For example: ADD @SRA,R4,123H; The assembler allows to define any one of possible types of the shift, or using one of the standard shift. Below brought all possible types of shift and operands, by means of which their are possible to assign. 6.3.1. Structured scheme of the performing shifts on ALB. ────────────────────────────────────────────────── ───────────┐ ┌──────────────────────── BP2 │ │ 4 x BC1 ═══ SLQ │<---------->│ RQ.0╟─────────────┐ ═══ │ │ │ │ │ │ │ │ ┌┬───────┬┐ │ SRQ │<---------->│RQ.15╟─┤│ RQ │├─┘ │ │ └┴───────┴┘ │ │ │ │ ┌┬───────┬┐ SRB │<---------->│RB.15╟─┤│ GPR[B]│├─┐ │ │ └┴───────┴┘ │ │ │ │ │ │ │ SLB │<---------->│ RB.0╟─────────────┘ │ │ 6.3.2. Standard types of shifts. ──────────────────────────────── │ logical │ arithmetical │ │ │ SRL │ SRA │ │ NO xor VO │ ┌┬───────┬┐ ┌──┐ │ │ ┌─┬───────┬┐ right │ 0─>││ GPR[B]││->│MC│ │ └─>│ │ GPR[B]││ │ └┴───────┴┘ └──┘ │ └─┴───────┴┘ │ │ │ SLL │ SLA │ │ │ ┌──┐ ┌┬───────┬┐ │ ┌─┬───────┬┐ left │ │MC│<-││ GPR[B]││<─ 0 │ │ │ GPR[B]││<── 0 │ └──┘ └┴───────┴┘ │ └─┴───────┴┘ When assign the double standard shift it is necessary to write accordingly SRWL SLWL SRWA SLWA. For example: ADD SRA,R4,0; XOR SLWL,RQ,1010101010101010%; 6.3.3. General types of shifts. ───────────────────────────────────── They Are Assigned by type of shift (SR - a right shift, SL - a left shift) and type of the shift. The Type of the shift is assigned by its number (refer to table for BP2_MI.A-6), specified through point directly for type of the shift , for example: ADD SR.3, R0, R5, R3; XOR SL.18, R0, 10; Point to the fact, the type of right shifts (SR) is assigned by number from 0 to 15 and the type of left shifts (SL) by number from 16 to 31. 6.4. Entering carry. ─────────────────── Entering carry is assigned in command of the first subgroup (ADD and SUB).This operand is unnecessary and is by default considered equal zero. In the event of evident inputting of the carrying its necessary to set it in quality of the last operand of the command. The Inputting of the operand of the carrying influences on the field MI(5-0) of controller shift m/c BP2 of microinstructions. Here follows to take into account that this field is responsible also for loading of register of marks RM and RN m/c BP2; so be cearful in simultaneous use the commands of the arithmetical adding(subtractions) and commands of the loading of register of marks, because it can occur the accompaniment of the undesirable input carrying that will distort the result. The Translator of the assembler do not checks the compatibility of the commands and a mistake under said event will not give. The following possible signals of the entering carry are exist: 1) Z - a signal of the logical zero; 2) RM_C - a bit C of register of the mark RM; 3) RN_C - a bit C of register of the mark RN. It possible to assign the inversion of these signals by means of last operator to inversions "NOT". The Examples: ADD R1,RQ,R5,RM_C; SUB RQ,R4,not Z; ADD @SRA,R5,10,not RN_C; The using of the operand of the carrying requires the full task of the command.