85 lines
5.3 KiB
Plaintext
85 lines
5.3 KiB
Plaintext
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┌─────────────────────────────────────────────────────╖
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│ 4. FIELD PIU (priority interruptions unit). ║
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╘═════════════════════════════════════════════════════╝
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The KM1804BH1 chip is 8-bit microprogramming scheme of the
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vector priority interruption that can be increased, which produces
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priority processing of inquiry for interruptions from eight buses for
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different devices. Fields that providing management work of PIU
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is brought below:
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Includes:
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KM1804BH1 chip:
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BH1_MI² - Microinstruction;
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EINS - Permit of the acceptance to instruction;
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EV - Permit of the constant issue from ROM vectors
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to DB (data bus).
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┌─────────╖
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│ BH1_MI² ║ MICROINSTRUCTIONS OF THE KM1804BH1 CHIP.
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╘═════════╝ ──────────────────────────────────────┘
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Purpose.
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The field of the KM1804BH1 chip (priority interruption unit).
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The correspondence between opcode and executed function is
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provided in table.
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┌────┬─────────────┬─────────────────────────────────────┐
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│ MI │ │ microinstr. executed in BH1 │
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│3210│ Mnemonics │ (with signal EINS = 0 ) │
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├────┼─────────────┼─────────────────────────────────────┤
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│0000│ RESET; │general clear │
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│0001│ RESET IR; │clear IR │
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│0010│ CLR IR,Val; │clear IR signal from buses of mask │
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│0011│ CLR IR,MR; │clear IR with MR control │
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│0100│ CLR IR,VR; │clear IR with VR control │
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│0101│ READ VR; │read VR │
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│0110│ READ SR; │read SR │
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│0111│ READ MR; │read MR │
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│1000│ │installation of MR │
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│1001│ LOAD SR,Val;│load SR │
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│1010│ CLR MR,Val; │bitwise clear MR │
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│1011│ SET MR,Val; │bitwise installation of MR │
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│1100│ RESET MR; │clear MR │
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│1101│ DI; │prohib. of the request for interrup. │
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│1110│ LOAD MR,Val;│load MR │
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│1111│ EI; │permit of the request for interrup. │
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└────┴─────────────┴─────────────────────────────────────┘
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The note.
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Values are entered in binary code, that indicated by the
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symbol '²'on the top of field identifier (IM²). When entering
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the new command in this field is written code of the general
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clear command, but signal EINS=1 that's why the instruction
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is not executed.
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┌─────────╖
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│ EINS ║ PERMIT THE INSTRUCTIONS ACCEPTANCE.
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╘═════════╝ ─────────────────────────────────┘
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Purpose.
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The permit the instruction acceptance. Provides acceptance ÉáºαÑΦÑ¡¿Ñ »α¿Ñ¼á ¿¡ßΓαπ¬μ¿¿. ÃíÑß»Ñ?¿óáÑΓ »α¿Ñ¼ ¬
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to perform the instructions given in field BH1_IM².
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Level : 0 - Active (microinstruction on BH1 is executed)
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1 - Passive (microinstruction on BH1 is not executed).
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The note.
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Values are entered in binary code.
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When entering the new command presenting the code of
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the command on KM1804BH1 chip is prohibited.
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┌─────────╖
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│ EV ║ PERMIT OF CONSTANT ISSUE FROM ROM VECTOR.
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╘═════════╝ ────────────────────────────────────────┘
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Purpose.
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The active level of the signal provides the issue 16-bit
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constant from 8-address vectors ROM on system bus
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data. The address for ROM is 3-bit vector, thet is issue
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by PIC (priority interruptions controller).
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Values of the constants, prestored in ROM, are loading
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when the system is adjusting.
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Level : 0 - Active (constant output)
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1 - Passive (constant is not output because outputs of ROM
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are found in one third condition).
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The note.
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Values are entered in binary code.
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When entering the new command issue of constants is prohibited.
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