197 lines
9.3 KiB
Plaintext
197 lines
9.3 KiB
Plaintext
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6. Arithmetic-logical commands.
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═══════════════════════════════
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The arithmetic-logical commands serves for performing some microinstruction
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as adding, subtractions, bitwise logical operation, operation of the shifts,
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loading, inversion of separate register in Arithmetic-Logical Unit (ALU),
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that is built on four microcircuits BC1 and one m/c BP2.
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In a whole there is 7 commands, formats of which will are considered in
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given section:
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1)ADD - arithmetical adding;
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2)SUB - arithmetical subtraction;
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3)OR - logical adding;
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4)AND - logical multiplying;
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5)XOR - logical subtraction (excluding "OR");
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6)NAND - logical multiplying in which first operand is taking
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with inversion;
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7)NXOR - logical subtraction in which result is inverted;
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Next will be considered:
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6.1. Assign of register shifts.
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6.2. Assign of the result receiver.
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6.3. Assign of operand, on which is executed some operation.
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6.4. Assign of the input carrying.
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6.1. Receiver of the result.
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────────────────────────────
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As receiver of the result can emerge the following operands:
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1) RQ - work registers of ALB;
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2) R0..R15 - one of the register of the general-purpose (RGP);
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3) RB - RGP, number of which is determined in RB;
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4) NIL - the empty receiver (the result is not saved, but can protrude on
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BD, as well as can be used flags, which are installed when the
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operations is perform).
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The assigning of the RB implies use of RGP, the number of which is kept
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in stood register RB.
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6.2. Operands, on which operation is assigned.
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────────────────────────────────────────────────
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Any one of described above commands allows to execute the
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actions on two operands and place the result in to operations
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register, in general event not coinsiding with operand, on which
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operation was executed. For example,
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ADD RQ,R1,R2;
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But often receiver of the result is simultaneously and one of the
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worker operand. Then possible lower writing of this operand twice,
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and assembler by itself will be undertake the task hipping an
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operand commands. For example:
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SUB RQ,1;
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Here is possible operands, which possible indicate when command assign:
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1) Z - "internal" zero, specially realization in
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BC1 chip is to protect data bus from frequent
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trivial information;
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2) RQ - work register of ALB;
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3) R0..R15 - one of the general-purpose register;
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4) RA,RB - GPR, number of which is determined in RA or RB;
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5) numeric constant;
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6) BUS_D - writing of such operand speaks of that, that
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operand will be scanned from data bus.
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6.3. Assign of shift register.
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──────────────────────────────
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6.3.1. Structured scheme of the shift performing on ALB.
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6.3.2. Standard types of shifts.
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6.3.3. General types of shifts.
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The arithmetic-logical block, on which is built ALU of microprocessor
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complex has as one of their own function possibility of simultaneously
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with execution one of the arithmetic-logical operation to produce the shift
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of the register-receiver. Control of shift type is realized by microinstruction,
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entering on entry MI(10-6) m/c BR2. Shift is assigned by microinstruction
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MI(8) m/c BH1. Herewith is possible to realize simultaneous shift of worke
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register RQ. For this purpose is necessary to place before operand of the
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shift the operator of the modification
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"@"
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which is indicates to assembler that is produced simultaneous shift of the
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register-receiver and work register RQ. For example:
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ADD @SRA,R4,123H;
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The assembler allows to define any one of possible types of the
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shift, or using one of the standard shift. Below brought all possible
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types of shift and operands, by means of which their are possible
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to assign.
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6.3.1. Structured scheme of the performing shifts on ALB.
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──────────────────────────────────────────────────
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───────────┐ ┌────────────────────────
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BP2 │ │ 4 x BC1
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═══ SLQ │<---------->│ RQ.0╟─────────────┐ ═══
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│ │ │
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│ │ │
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│ │ ┌┬───────┬┐ │
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SRQ │<---------->│RQ.15╟─┤│ RQ │├─┘
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│ │ └┴───────┴┘
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│ │
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│ │ ┌┬───────┬┐
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SRB │<---------->│RB.15╟─┤│ GPR[B]│├─┐
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│ │ └┴───────┴┘ │
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│ │ │
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│ │ │
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SLB │<---------->│ RB.0╟─────────────┘
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│ │
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6.3.2. Standard types of shifts.
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────────────────────────────────
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│ logical │ arithmetical
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│ │
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│ SRL │ SRA
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│ │ NO xor VO
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│ ┌┬───────┬┐ ┌──┐ │ │ ┌─┬───────┬┐
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right │ 0─>││ GPR[B]││->│MC│ │ └─>│ │ GPR[B]││
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│ └┴───────┴┘ └──┘ │ └─┴───────┴┘
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│ │
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│ SLL │ SLA
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│ │
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│ ┌──┐ ┌┬───────┬┐ │ ┌─┬───────┬┐
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left │ │MC│<-││ GPR[B]││<─ 0 │ │ │ GPR[B]││<── 0
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│ └──┘ └┴───────┴┘ │ └─┴───────┴┘
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When assign the double standard shift it is necessary to write
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accordingly SRWL SLWL SRWA SLWA.
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For example: ADD SRA,R4,0;
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XOR SLWL,RQ,1010101010101010%;
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6.3.3. General types of shifts.
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─────────────────────────────────────
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They Are Assigned by type of shift (SR - a right shift, SL - a left
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shift) and type of the shift. The Type of the shift is assigned by its
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number (refer to table for BP2_MI.A-6), specified through point
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directly for type of the shift , for example:
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ADD SR.3, R0, R5, R3;
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XOR SL.18, R0, 10;
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Point to the fact, the type of right shifts (SR) is assigned by number
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from 0 to 15 and the type of left shifts (SL) by number from 16 to 31.
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6.4. Entering carry.
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───────────────────
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Entering carry is assigned in command of the first subgroup (ADD and
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SUB).This operand is unnecessary and is by default considered equal zero.
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In the event of evident inputting of the carrying its necessary to set it
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in quality of the last operand of the command. The Inputting of the
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operand of the carrying influences on the field MI(5-0) of controller shift
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m/c BP2 of microinstructions. Here follows to take into account that this
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field is responsible also for loading of register of marks RM and RN m/c
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BP2; so be cearful in simultaneous use the commands of the arithmetical
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adding(subtractions) and commands of the loading of register of marks,
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because it can occur the accompaniment of the undesirable input carrying
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that will distort the result. The Translator of the assembler do not checks
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the compatibility of the commands and a mistake under said event will not give.
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The following possible signals of the entering carry are exist:
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1) Z - a signal of the logical zero;
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2) RM_C - a bit C of register of the mark RM;
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3) RN_C - a bit C of register of the mark RN.
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It possible to assign the inversion of these signals by means of last
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operator to inversions "NOT". The Examples:
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ADD R1,RQ,R5,RM_C;
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SUB RQ,R4,not Z;
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ADD @SRA,R5,10,not RN_C;
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The using of the operand of the carrying requires the full task of the
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command.
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