           ┌─────────────────────────────────────────────╖
           │ 2.Field ALU (data processing unit).         ║
           ╘═════════════════════════════════════════════╝

    The data processing unit (hereinafter ALU) of proposed systems 
    is built with use of the following functioning junctions:
    
    1) 4  microprocessor  sections  KM1804BC1, which form the 
       16-bit based ALU.
    2) Condition control  and shift Scheme KM1804BP2, which is                               ÀσÑ¼á π»αáó½Ñ¡¿∩ ß«ßΓ«∩¡¿Ñ¼ ¿ ßñó¿úá¼¿ èÔ1804éÉ2, ¬«Γ«αá∩
       intended to joint  work with processor element BC1 and 
       provides closing of data around microprocessor section. 
       Given  microcircuit  provides  the  functions  of   the 
       register of the conditions and forming of the signal of 
       the  carrying,  mix  of  the sources of the input carry 
       signal ALU,  organizes 32 types of shift (arithmetical, 
       logical, round-robin),  which  can  be usual or double-
       length, contains two 4-bit  register  of the condition, 
       executes 16 operations  on  forming  the  signal of the 
       condition. 
    3) Microcircuit of the framing:
        4-bit registers of operands (RAA,RAB);
        The Multiplexers of select of the source operand, which 
        allows to address the registers participating in operations 
        ALU or from MIM, or on the address, keeping in RAA and RAB.

  To  manage afore-mentioned  device, each command in MIM contains 
  the following fields.

 Includes:
     Microcircuit KM1804BC1:
                BC1_MI²  - operation in BC1;
                A,B      - number of ALU registers;
                OEY      - acception for issues of result from ALU;

                Microcircuit KM1804BP2:
                BP2_MI²  - operation in BP2;
                E.ZNCV   - permit of per-bit marks writing in RM;
                OECT     - permit an issue of the code term;
                CEM      - permit writing the marks in RM;
                CEN      - permit writing the marks in RN;
                SE       - permit of the shift performing;

                Microcircuits of the framing:
                MSA      - source of operand in ALU (MIM or RA);
                MSB      - source of operand in ALU (MIM or RB);
                EWA      - writing in operand registers RA;
                EWB      - writing in operand registers RB.



 ┌────────╖
 │ BC1_MI²║  THE MICROINSTRUCTION FIELD OF THE MICROCIRCUIT BC1.
 ╘════════╝   ──────────────────────────────────────────────────┘
 Purpose.
           Assign  the operation executed in ALU.  Given  field contains     
           several sections (the flap), each defines the nature      
           of executed operations.           
                1)      Field of the result receiver  in ALU;
                2)      Field of operation in ALU;
                3)      Field of operation in ALU.
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).


 ┌───────────╖
 │BC1_MI².876║  THE RECEIVER OF THE OPERATION RESULT IN ALU.
 ╘═══════════╝   ───────────────────────────────────────────┘
 Purpose.
           Field of the result receiver in ALU (bits 8,7,6).
           Defines where fits result of the operations.
           ┌───┬───────────────────────────────────────────────────┐
           │MI │                                                   │
           │876│ where will get the result of operation processing │
           ├───┼───────────────────────────────────────────────────┤
           │000│   F -> Q                                          │
           │001│    result of operations in ALU does not place in  │
           │   │    any internal registers and is used only for    │
           │   │    indirect effect, for instance restore all      │
           │   │    operation flags, or output the result of       │
           │   │    operation on the data bus.                     │                        │
           │010│      F -> B and result does not output on bus,    │
           │   │    but value of the register - an operand A       │
           │011│      F -> B                                       │
           │100│      F/2 -> B, Q/2 -> Q                           │
           │101│      F/2 -> B                                     │
           │110│      2F -> B,  2Q -> Q                            │
           │111│      2F -> B                                      │
           └───┴───────────────────────────────────────────────────┘
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).
           When entered a new command the code 001 became assigned.


 ┌───────────╖
 │BC1_MI².543║  OPERATIONS IN ALU.
 ╘═══════════╝   ─────────────────┘
 Purpose.
           The field of operations in ALU (bits 5,4,3). Defines 
           nature of the transformation on chosen operand.
           ┌───┬──────┬───────────────┐
           │MI │mnemo-│   operation   │
           │543│ nics │    in ALU     │
           ├───┼──────┼───────────────┤
           │000│ ADD  │   R+S+CI      │
           │001│ SUB  │   S-R-1+CI    │
           │010│ SUB  │   R-S-1+CI    │
           │011│ OR   │   R or S      │
           │100│ AND  │   R and S     │
           │101│ NAND │   not(R) and S│
           │110│ XOR  │   R xor S     │
           │111│ NXOR │   not(R xor S)│
           └───┴──────┴───────────────┘
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).
           When entered a new command the code 000 became assigned.


 ┌───────────╖
 │BC1_MI².210║  FIELD OF THE OPERATION OPERANDS IN ALU.
 ╘═══════════╝   ──────────────────────────────────────┘
 Purpose.
           The field of operations in ALU (bits 2,1,0). Defines
           operands, which participate in operations performing.
           ┌───┬───────────┬──────┐
           │MI │           │      │
           │210│ mnemonics │R    S│
           ├───┼───────────┼──────┤
           │000│ Rx , RQ ; │A    Q│
           │001│ Rx , Rx ; │A    B│
           │010│ Z  , RQ ; │Z    Q│
           │011│ Z  , Rx ; │Z    B│
           │100│ Z  , Rx ; │Z    A│
           │101│ Val, Rx ; │D    A│
           │110│ Val, RQ ; │D    Q│
           │111│ Val, Z  ; │D    Z│
           └───┴───────────┴──────┘
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).
           When entered a new command the code 000 became assigned.


 ┌────────╖
 │  A, B  ║  NUMBERS OF REGISTERS IN ALU, WHICH ARE USED IN OPERATION.
 ╘════════╝   ────────────────────────────────────────────────────────┘
 Purpose.
           Fields define numbers of registers in  ALU,  which are 
           used  in performing  an operation. Values  from this field 
           are  accordingly output on  entrances A and B  of the chip 
           BC1. The switching condition of these flap to microcircuit 
           BC1 are signals on the operands source select multiplexors
           MSA=0 and MSB=0.
 The note.
           Values are entered in hexadecimal code.
           When entered a new command then assigned zero GPRs 
           (general-purpose registers).

 ┌────────╖
 │  OEY   ║  PERMIT FOR THE RESULT OUTPUT.
 ╘════════╝   ────────────────────────────┘
 Purpose.
           Permit for output of the result from ALU (BC1) on  
           system data bus.
 Level  :  0 - Active  (output permit)
           1 - Passive (output prohibited).
 The note.
           Values are entered in binary code.
           While entering a new command the outputing of the 
           operations result in ALU is prohibited.


 ┌─────────╖
 │ BP2_MI² ║  FIELD OF THE MICROINSTRUCTION IN THE BP2 CHIP.
 ╘═════════╝   ─────────────────────────────────────────────┘
 Purpose.
           It will assign microinstruction which is executed in 
           device of condition and shift management  KM1804BP2,
           which  provides a data closing around microprocessor 
           section   (KM1804BC1). This  field  contains several 
           sections:
              1) The management field of the signal carrying CI;
              2) The control field of the shift performing;
              3) Field which controls the output of the code 
                  condition and loading of the register marks.
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).


 ┌──────────╖
 │BP2_MI².CB║  THE MANAGEMENT OF CI SIGNAL.
 ╘══════════╝   ───────────────────────────┘
 Purpose.
           Field that controls signal of carrying CI (bits 12,11). 
           Values  of this field allows to commute the different 
           signals on entry Si of ALU sections.
     ┌──┬──────┬───────────────────────────────────────────────────────┐
     │MI│mnemo-│                                                       │
     │CB│ nics │         shift, that entered in ALU entry              │
     ├──┼──────┼───────────────────────────────────────────────────────┤
     │00│  Z   │                    0                                  │
     │01│not Z │                    1                                  │
     │10│      │               is not used                             │
     │11│ RM_C │signal of carrying is assigned as output of À registers│
     │  │ RN_C │on the marks RM and RN in the following order:         │
     │  │not   │under MI.5 = 1 with RM.C, otherwise with RN.C;         │
     │  │  RM_C│under MI.321 = 100 signals transforms by inversion     │
     │  │  RN_C│under any other combinations - without it              │
     └──┴──────┴───────────────────────────────────────────────────────┘
 The note.
           Values are entered in binary code, that indicated by the  
           symbol '²'on the top of field identifier  (IM²).
           When entered a new command the code 00 became assigned.


 ┌───────────╖
 │BP2_MI².A-6║  FIELD OF SHIFT CONTROL.
 ╘═══════════╝   ──────────────────────┘
 Purpose.
           Field that controlling the shift performing (bits 10-6).
 ┌─────┬────┬───────────────┬───────────────────────────────────────────┐
 │     │    │               │   forming the shift signals for the ALU   │
 │  MI │    │               │      registers (with signal SE = 0 )      │
 │A9876│dec.│  mnemonics    ├──────────────┬──────────┬─────────────────┤
 │     │    │               │  on register │  on reg. │ load of C flag  │
 │     │    │               │ receiv. resu.│    RQ    │ in reg. mark RM │
 ├─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┤
 │                      R I G H T   S H I F T S                         │
 ├─────┬────┬───────────────┬──────────────┬──────────┬─────────────────┤
 │00000│ 00 │        SR.0   │SRB:=0        │SRQ:=0    │      no         │
 │00001│ 01 │        SR.1   │SRB:=1        │SRQ:=1    │      no         │
 │00010│ 02 │ SRL  (SR.2)   │SRB:=0        │SRQ:=RM.N │   RM.C:=SRB     │
 │00011│ 03 │        SR.3   │SRB:=1        │SRQ:=SRB  │      no         │
 │00100│ 04 │        SR.4   │SRB:=RM.C     │SRQ:=SRB  │      no         │
 │00101│ 05 │        SR.5   │SRB:=RM.N     │SRQ:=SRB  │      no         │
 │00110│ 06 │        SR.6   │SRB:=0        │SRQ:=SRB  │      no         │
 │00111│ 07 │ SRWL (SR.7)   │SRB:=0        │SRQ:=SRB  │   RM.C:=SRQ     │
 │01000│ 08 │        SR.8   │SRB:=SRB      │SRQ:=SRQ  │   RM.C:=SRB     │
 │01001│ 09 │        SR.9   │SRB:=RM.C     │SRQ:=SRQ  │   RM.C:=SRB     │
 │01010│ 10 │        SR.10  │SRB:=SRB      │SRQ:=SRQ  │      no         │
 │01011│ 11 │        SR.11  │SRB:=CO       │SRQ:=SRB  │      no         │
 │01100│ 12 │        SR.12  │SRB:=RM.C     │SRQ:=SRB  │   RM.C:=SRQ     │
 │01101│ 13 │        SR.13  │SRB:=SRQ      │SRQ:=SRB  │   RM.C:=SRQ     │
 │01110│ 14 │SRA SRWA(SR.14)│SRB:=NO xor VO│SRQ:=SRB  │      no         │
 │01111│ 15 │        SR.15  │SRB:=SRQ      │SRQ:=SRB  │      no         │
 ├─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┤
 │                       L E F T  S H I F T S                           │
 ├─────┬────┬───────────────┬──────────────┬──────────┬─────────────────┤
 │10000│ 16 │ SLL  (SL.16)  │SLB:=0        │SLQ:=0    │   RM.C:=SLB     │
 │10001│ 17 │        SL.17  │SLB:=1        │SLQ:=1    │   RM.C:=SLB     │
 │10010│ 18 │ SLA  (SL.18)  │SLB:=0        │SLQ:=0    │      no         │
 │10011│ 19 │        SL.19  │SLB:=1        │SLQ:=1    │      no         │
 │10100│ 20 │ SLWL (SL.20)  │SLB:=SLQ      │SLQ:=0    │   RM.C:=SLB     │
 │10101│ 21 │        SL.21  │SLB:=SLQ      │SLQ:=1    │   RM.C:=SLB     │
 │10110│ 22 │ SLWA (SL.22)  │SLB:=SLQ      │SLQ:=0    │      no         │
 │10111│ 23 │        SL.23  │SLB:=SLQ      │SLQ:=1    │      no         │
 │11000│ 24 │        SL.24  │SLB:=SLB      │SLQ:=SLQ  │   RM.C:=SLB     │
 │     │    │               │              │          │                 │
 │11001│ 25 │        SL.25  │SLB:=RM.C     │SLQ:=SLB  │   RM.C:=SLB     │
 │11010│ 26 │        SL.26  │SLB:=SLB      │SLQ:=SLB  │      no         │
 │11011│ 27 │        SL.27  │SLB:=RM.C     │SLQ:=0    │      no         │
 │11100│ 28 │        SL.28  │SLB:=SLQ      │SLQ:=RM.C │   RM.C:=SLB     │
 │11101│ 29 │        SL.29  │SLB:=SLQ      │SLQ:=SLB  │   RM.C:=SLB     │
 │11110│ 30 │        SL.30  │SLB:=SLQ      │SLQ:=RM.C │      no         │
 │11111│ 31 │        SL.31  │SLB:=SLQ      │SLQ:=SLB  │      no         │
 └─────┴────┴───────────────┴──────────────┴──────────┴─────────────────┘
 The note.
          Values are  entered in  binary code, that indicated by the  
          symbol '²'on the top of field identifier  (IM²).
          When entered a new command the code 00000 became assigned.


 ┌───────────╖
 │BP2_MI².5-0║  CONDITION CT OR LOADING REGISTER OF MARKS.
 ╘═══════════╝   ─────────────────────────────────────────┘
 Purpose.
           The field that controls the leaving of  condition  code  and  
           boot of register marks (bits 5-0).The contents of the given 
           field can be interpretated in a different type:
             1)   forming the signal of the logical condition
                  (at signal OECT=0);
             2)   operations of the loading register marks.
                  (at signal OECT=1);
           ┌──────┬───┬──────┬────────────────────────────────────────┐
           │  MI  │   │mnemo-│  forming signal of a logical condition │
           │543210│dec│ nics │        (at signal OECT = 0 )           │
           │──────┼───┼──────┼────────────────────────────────────────┤
           │000000│ 00│      │CT:=RN.Z  or (RN.N  xor RN.V);          │
           │000001│ 01│      │CT:=not(RN.N  xor RN.V) and not(RN.Z);  │
           │000010│ 02│      │CT:=RN.N xor RN.V;                      │
           │000011│ 03│      │CT:=not(RN.N xor RN.V);                 │
           │000100│ 04│ RN_Z │CT:=RN.Z;                               │
           │000101│ 05│      │CT:=not(RN.Z);                          │
           │000110│ 06│ RN_V │CT:=RN.V;                               │
           │000111│ 07│      │CT:=not(RN.V);                          │
           │001000│ 08│      │CT:=RN.C or RN.Z;                       │
           │001001│ 09│      │CT:=not(RN.C) and not(RN.Z);            │
           │001010│ 10│ RN_C │CT:=RN.C;                               │
           │001011│ 11│      │CT:=not(RN.C);                          │
           │001100│ 12│      │CT:=not(RN.C) or RN.Z;                  │
           │001101│ 13│      │CT:=RN.C and not(RN.Z);                 │
           │001110│ 14│      │CT:=NO xor RM.N;                        │
           │001111│ 15│      │CT:=not(NO xor RM.N);                   │
           │010000│ 16│      │CT:=RgN.Z or (RN.N xor RN.V);           │
           │010001│ 17│      │CT:=not(RN.N xor RN.V) and not(RN.Z);   │
           │010010│ 18│      │CT:=RN.N xor RN.V;                      │
           │010011│ 19│      │CT:=not(RN.N xor RN.V);                 │
           │010100│ 20│      │CT:=RN.Z;                               │
           │010101│ 21│      │CT:=not(RN.Z);                          │
           │010110│ 22│      │CT:=RN.V;                               │
           │010111│ 23│      │CT:=not(RN.V);                          │
           │011000│ 24│      │CT:=RN.C or RN.Z;                       │
           │011001│ 25│      │CT:=not(RN.C) and not(RN.Z);            │
           │011010│ 26│      │CT:=RN.C;                               │
           │011011│ 27│      │CT:=not(RN.C);                          │
           │011100│ 28│      │CT:=not(RN.C) or RN.Z;                  │
           │011101│ 29│      │CT:=RN.C and not(RN.Z);                 │
           │011110│ 30│ RN_N │CT:=RN.N;                               │
           │011111│ 31│      │CT:=not(NO xor RM.N);                   │
           │100000│ 32│      │CT:=RM.Z or (RM.N xor RM.V);            │
           │100001│ 33│      │CT:=not(RM.N xor RM.V) and not(RM.Z);   │
           │100010│ 34│      │CT:=RM.N xor RM.V;                      │
           │100011│ 35│      │CT:=not(RM.N xor RM.V);                 │
           │100100│ 36│ RM_Z │CT:=RM.Z;                               │
           │100101│ 37│      │CT:=not(RM.Z);                          │
           │100110│ 38│ RM_V │CT:=RM.V;                               │
           │100111│ 39│      │CT:=not(RM.V);                          │
           │101000│ 40│      │CT:=RM.C or RM.Z;                       │
           │101001│ 41│      │CT:=not(RM.C) and not(RM.Z);            │
           │101010│ 42│ RM_C │CT:=RM.C;                               │
           │101011│ 43│      │CT:=not(RM.C);                          │
           │101100│ 44│      │CT:=not(RM.C) or RM.Z;                  │
           │101101│ 45│      │CT:=RM.C and not(RM.Z);                 │
           │101110│ 46│ RM_N │CT:=RM.N;                               │
           │101111│ 47│      │CT:=not(RM.N);                          │
           │110000│ 48│      │CT:=ZO or (NO xor VO);                  │
           │110001│ 49│      │CT:=not(NO xor VO) and not(ZO);         │
           │110010│ 40│ NXORV│CT:=NO xor VO;                          │
           │110011│ 51│      │CT:=not(NO xor VO);                     │
           │110100│ 52│ ZO   │CT:=ZO;                                 │
           │110101│ 53│      │CT:=not(ZO);                            │
           │110110│ 54│ VO   │CT:=VO;                                 │
           │110111│ 55│      │CT:=not(VO);                            │
           │111000│ 56│      │CT:=CO or ZO;                           │
           │111001│ 57│ ZORC │CT:=not(CO) and not(ZO);                │
           │111010│ 58│ CO   │CT:=CO;                                 │
           │111011│ 59│      │CT:=not(CO);                            │
           │111100│ 60│      │CT:=not(CO) or ZO;                      │
           │111101│ 61│      │CT:=CO and not(ZO);                     │
           │111110│ 62│ NO   │CT:=NO;                                 │
           │111111│ 63│      │CT:=not(NO);                            │
           └──────┴───┴──────┴────────────────────────────────────────┘
 The note: if mnemonics is not given, than it is necessary to use command FIELD.
 The note.
          Values are  entered in  binary code, that indicated by the  
          symbol '²'on the top of field identifier  (IM²).
          When entered a new command the code 000000 became assigned.           
           ┌──────┬───┬─────────────────┬────────────────────────────────────────┐
           │  MI  │   │                 │operations for loading of register marks│
           │      │   │                 ├───────────────────┬────────────────────┤
           │543210│dec│   mnemonics     │ operation in RN   │operation in RM when│
           │      │   │                 │   (when CEN=0)    │ CEM, E.C,Z,N,V=0   │
           ├──────┼───┼─────────────────┼───────────────────┼────────────────────┤
           │000000│ 00│ LOAD RN,RM;     │    RN:=RM;        │    no loading      │
           │000001│ 01│ LOAD RM,NZ;     │    RN:=1111       │    RM:=1111        │
           │      │   │ LOAD RN,NZ;     │                   │                    │
           │000010│ 02│ LOAD RM,RN;     │    RN <--> RM     │    RM:=RN          │
           │000011│ 03│ LOAD RM,Z;      │    RN:=0000       │    RM:=0000        │
           │      │   │ LOAD RN,Z;      │                   │                    │
           │000100│ 04│ LOAD RN,FLAGS;  │    RN:=FLAGS      │ Z:=ZO N:=NO C<-->V │
           │000101│ 05│                 │    RN:=FLAGS      │    RM:=not RM      │
           │000110│ 06│ LOAD  RM,FLAGS;  RN:=FLAGS except   │    RM:=FLAGS       │
           │000111│ 07│ LOAD @RN,FLAGS;  RN.V:=RN.V xor VO  │    RM:=FLAGS       │
           │001000│ 08│ LOAD @RM,FLAGS; │    RN.Z:=0         RM:=FLAGS except    │
           │001001│ 09│                 │    RN.Z:=1         RM.C:=not CO        │
           │001010│ 10│                 │    RN.C:=0        │    RM:=FLAGS       │
           │001011│ 11│                 │    RN.C:=1        │    RM:=FLAGS       │
           │001100│ 12│                 │    RN.N:=0        │    RM:=FLAGS       │
           │001101│ 13│                 │    RN.N:=1        │    RM:=FLAGS       │
           │001110│ 14│                 │    RN.V:=0        │    RM:=FLAGS       │
           │001111│ 15│                 │    RN.V:=1        │    RM:=FLAGS       │
           │010000│ 16│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010001│ 17│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010010│ 18│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010011│ 19│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010100│ 20│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010101│ 21│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010110│ 22│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │010111│ 23│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011000│ 24│                  RN:=FLAGS except    RM:=FLAGS except    │
           │011001│ 25│                  RN.C:=not CO        RM.C:=not CO        │
           │011010│ 26│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011011│ 27│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011100│ 28│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011101│ 29│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011110│ 30│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │011111│ 31│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100000│ 32│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100001│ 33│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100010│ 34│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100011│ 35│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100100│ 36│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100101│ 37│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100110│ 38│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │100111│ 39│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101000│ 40│                  RN:=FLAGS except    RM:=FLAGS except    │
           │101001│ 41│                  RN.C:=not CO        RM.C:=not CO        │
           │101010│ 42│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101011│ 43│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101100│ 44│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101101│ 45│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101110│ 46│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │101111│ 47│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110000│ 48│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110001│ 49│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110010│ 40│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110011│ 51│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110100│ 52│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110101│ 53│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110110│ 54│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │110111│ 55│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111000│ 56│                  RN:=FLAGS except    RM:=FLAGS except    │
           │111001│ 57│                  RN.C:=not CO        RM.C:=not CO        │
           │111010│ 58│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111011│ 59│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111100│ 60│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111101│ 61│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111110│ 62│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           │111111│ 63│                 │    RN:=FLAGS      │    RM:=FLAGS       │
           └──────┴───┴─────────────────┴───────────────────┴────────────────────┘
 The note: if mnemonics is not given, than it is necessary to use command FIELD;
           the torn lines in table mean that is given one command 
           for two codes.   
 The note.
          Values are  entered in  binary code, that indicated by the  
          symbol '²'on the top of field identifier  (IM²).
          When entered a new command the code 000000 became assigned.           


 ┌─────────╖
 │E.C,Z,N,V║  BITWISE PERMIT THE RECORDING IN REGISTER RM.
 ╘═════════╝   ───────────────────────────────────────┘
 Purpose.
           The permit of  writing of the marks in one bit of the 
           marks register (RM) of BP2 chip. Record is provided 
           when signal SEM=0
 Level  :  0 - Active  (writing is permited)
           1 - Passive (writing is prohibited).
 The note.
        Values are entered in binary code.
        When entering the new command then bitwise writing for all marks is resolved.



 ┌─────────╖
 │  OECT   ║  PERMIT THE ISSUE OF THE TERM CODE ON CT OUTPUT.
 ╘═════════╝   ──────────────────────────────────────────────┘
 Purpose.
           Permit  the  issue of the  term code  on CT output of the  
           KM1804BP2 chip. Herewith  the formed  signal on CT output  
           is  defined by  code in  field  BP2_MI².5-0  (bits 5-0 of 
           the  microinstruction codes for the BP2 chip). The signal 
           of the logical condition is formed when OECT=0. 
 Level  :
           0 - Active  (forming permit)
           1 - Passive (forming prohibited).
 The note.
           Values are entered in binary code.
           When  entering  the  new  command  the forming of logical 
           conditions is prohibited.

 ┌─────────╖
 │ CEN,CEM ║  PERMIT OF MARKS WRITING IN REGISTERS RN/RM.
 ╘═════════╝   ──────────────────────────────────────────┘
 Purpose.
           Permit of marks writing in registers RN/RM 
           of KM1804BP2 chip.
 Level  :  0 - Active  (writing permit)
           1 - Passive (writing prohibited).
 The note.
           Values are entered in binary code.
           When entering the new command record in registers prohibited..

 ┌─────────╖
 │   SE    ║  PERMIT OF THE SHIFT PERFORMING.
 ╘═════════╝   ──────────────────────────────┘
 Purpose.
           The permit of the shift performing in KM1804BP2 chip.
 Level  :  0 - Active  (shift permit)
           1 - Passive (shift prohibited).
 The note.
           Values are entered in binary code.
           When entering the new command the shifts are prohibited.

 ┌─────────╖
 │ MSA,MSB ║  CHOICE A SOURCES OF THE OPERAND ADDRESS.
 ╘═════════╝   ───────────────────────────────────────┘
 Purpose.
           Choice of the source operand in ALU (MIM  or  RA). Field contains
           the  signals  of the  multiplexer  that  controls a choice of the
           address source of operand for operation in ALU.
 Value  :   0 - The number of the KM1804BC1 chip register is 
                extracted from MIM;
            1 - The number of the KM1804BC1 chip register is 
                extracted from external register.
 The note.
           Values are entered in binary code.
           When entering a new command  the multiplexer chooses a number 
           of the register from microinstructions memory.


 ┌─────────╖
 │  EWA,EWB║  WRITING INFORMATION IN OPERAND SELECT REGISTERS IN ALU.
 ╘═════════╝   ─────────────────────────────────────────────────────────┘
 Purpose.
           The low-level signal provides record of information from 
           system  bus  that  is  given  in 4-bit registers (RA,RB) 
           of the  operand  choice  in  ALU.  The number buses bits 
           that  is  used  for  loading  registers are defined when 
           adjusting the system.
 Level  :  0 - Active  (write)
           1 - Passive (storage).
 The note.
       Values are entered in binary code.
       When entering the new command the record in registers are prohibited.
