4 Commits

Author SHA1 Message Date
Rhinemann 0f94f6d37a Minor rewrites. 2023-06-27 16:43:18 +03:00
Rhinemann 9fedc98310 Implemented input_handler function. 2023-06-27 16:40:09 +03:00
Rhinemann b3c5011c11 Revamped function scopes. 2023-06-27 15:53:20 +03:00
Rhinemann f477c6f9e1 binary_subtraction_1_complement initial commit. 2023-06-27 15:34:39 +03:00
2 changed files with 64 additions and 46 deletions
+39 -22
View File
@@ -67,8 +67,8 @@ def get_memory(variable_name: str) -> list[bool]:
print(f"[ERROR] The {variable_name} may contain only 1-s and 0-s!")
def binary_sum(first_term: BasicRegister, second_term: BasicRegister, return_remainder: bool = False)\
-> BasicRegister | tuple[BasicRegister, int]:
def binary_sum(first_term: BasicRegister, second_term: BasicRegister, return_remainder: bool = False) \
-> BasicRegister or tuple[BasicRegister, int]:
"""
Sums two registers' values.
@@ -79,30 +79,47 @@ def binary_sum(first_term: BasicRegister, second_term: BasicRegister, return_rem
:return: Register containing the sum or the tuple containing the register and carried radix.
:rtype: BasicRegister | tuple[BasicRegister, int]
"""
size_a = len(first_term)
size_b = len(second_term)
required_size = max(size_a, size_b)
a = first_term
b = second_term
if size_a != size_b:
a = a.adjusted_by_size(required_size)
b = b.adjusted_by_size(required_size)
c = BasicRegister([False] * required_size)
result = BasicRegister([False] * len(first_term))
carry = False
for i in range(required_size - 1, 0, -1):
current_bit_sum = a.memory[i] + b.memory[i] + carry
for i in range(len(first_term) - 1, 0, -1):
current_bit_sum = first_term.memory[i] + second_term.memory[i] + carry
carry = bool(current_bit_sum & 2)
c.memory[i] = bool(current_bit_sum & 1)
result.memory[i] = bool(current_bit_sum & 1)
final_bit_sum = a.memory[0] + b.memory[0] + carry
c.memory[0] = bool(final_bit_sum & 1)
final_bit_sum = first_term.memory[0] + second_term.memory[0] + carry
result.memory[0] = bool(final_bit_sum & 1)
if return_remainder:
return c, carry
final_carry = bool(final_bit_sum & 2)
return result, final_carry
else:
return c
return result
def binary_subtraction(first_term: BasicRegister, second_term: BasicRegister) -> BasicRegister:
second_term.reverse()
result: BasicRegister
final_carry: bool
result, final_carry = binary_sum(first_term, second_term, True)
if final_carry:
return binary_sum(result, BasicRegister([True] * len(result)))
else:
result.reverse()
return result
def align_registers(first_register: BasicRegister, second_register: BasicRegister) \
-> tuple[BasicRegister, BasicRegister]:
first_size = len(first_register)
second_size = len(second_register)
required_size = max(first_size, second_size)
if first_size != second_size:
return first_register.adjusted_by_size(required_size), second_register.adjusted_by_size(required_size)
else:
return first_register, second_register
+25 -24
View File
@@ -1,31 +1,32 @@
import bitutilities as bu
import timeit
def input_handler(first_register: bu.BasicRegister, second_register: bu.BasicRegister):
first_register, second_register = bu.align_registers(first_register, second_register)
print()
print(first_register)
print(second_register)
while True:
print()
match input("Choose the operation:\n[a]ddition, [s]ubtraction, [m]ultiplication, [d]ivision, [q]uit\n>>> "):
case "a":
print(f"Sum:\n{bu.binary_sum(first_register, second_register)}")
case "s":
print(f"Subtraction:\n{bu.binary_subtraction(first_register, second_register)}")
case "m":
pass
case "d":
pass
case "q":
exit()
case _:
print("Not an available operation, try again.")
if __name__ == '__main__':
reg: bu.BasicRegister = bu.BasicRegister(bu.get_memory("memory"))
print()
print("Register 1:")
print(reg)
print()
reg2: bu.BasicRegister = bu.BasicRegister(bu.get_memory("more memory"))
print()
print("Register 2:")
print(reg2)
print()
reg3: bu.BasicRegister = bu.binary_sum(reg, reg2)
print()
print("Sum:")
print(reg3)
carry_sum_test: tuple[bu.BasicRegister, int] = bu.binary_sum(reg, reg2, True)
print()
print("Sum & carry:")
# print(type(carry_sum_test))
print(carry_sum_test)
input_handler(reg, reg2)