diff --git a/src/bit_utilities.rs b/src/bit_utilities.rs
index 8784335..1c1a513 100644
--- a/src/bit_utilities.rs
+++ b/src/bit_utilities.rs
@@ -53,8 +53,10 @@ impl BasicRegister {
         let bits_shifted: usize = bits_shifted_default.unwrap_or(1) as usize;
 
         let mut shifted_bits: VecDeque<bool> = [].into();
-        (0..bits_shifted).for_each(|_| shifted_bits.push_back(self.memory.pop_front().unwrap()));
-        (0..bits_shifted).for_each(|_| self.memory.push_back(shift_in_value));
+        for _i in 0..bits_shifted {
+            shifted_bits.push_back(self.memory.pop_front().unwrap());
+            self.memory.push_back(shift_in_value)
+        }
 
         shifted_bits
     }
@@ -68,8 +70,10 @@ impl BasicRegister {
         let bits_shifted: usize = bits_shifted_default.unwrap_or(1) as usize;
 
         let mut shifted_bits: VecDeque<bool> = [].into();
-        (0..bits_shifted).for_each(|_| shifted_bits.push_back(self.memory.pop_back().unwrap()));
-        (0..bits_shifted).for_each(|_| self.memory.push_front(shift_in_value));
+        for _i in 0..bits_shifted {
+            shifted_bits.push_back(self.memory.pop_back().unwrap());
+            self.memory.push_front(shift_in_value)
+        }
 
         shifted_bits
     }