Rewrote bit shifts.
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81f190dc60
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289b87a556
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@ -53,8 +53,10 @@ impl BasicRegister {
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let bits_shifted: usize = bits_shifted_default.unwrap_or(1) as usize;
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let mut shifted_bits: VecDeque<bool> = [].into();
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(0..bits_shifted).for_each(|_| shifted_bits.push_back(self.memory.pop_front().unwrap()));
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(0..bits_shifted).for_each(|_| self.memory.push_back(shift_in_value));
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for _i in 0..bits_shifted {
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shifted_bits.push_back(self.memory.pop_front().unwrap());
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self.memory.push_back(shift_in_value)
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}
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shifted_bits
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}
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@ -68,8 +70,10 @@ impl BasicRegister {
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let bits_shifted: usize = bits_shifted_default.unwrap_or(1) as usize;
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let mut shifted_bits: VecDeque<bool> = [].into();
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(0..bits_shifted).for_each(|_| shifted_bits.push_back(self.memory.pop_back().unwrap()));
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(0..bits_shifted).for_each(|_| self.memory.push_front(shift_in_value));
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for _i in 0..bits_shifted {
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shifted_bits.push_back(self.memory.pop_back().unwrap());
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self.memory.push_front(shift_in_value)
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}
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shifted_bits
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}
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