2023-06-26 00:26:09 +03:00
|
|
|
from collections import deque
|
2023-06-28 14:49:35 +03:00
|
|
|
from typing import Tuple, List, Any
|
|
|
|
|
2023-06-26 21:58:24 +03:00
|
|
|
from typing_extensions import Self
|
2023-06-28 12:36:02 +03:00
|
|
|
from lib.prettytable import PrettyTable
|
2023-06-26 00:26:09 +03:00
|
|
|
|
|
|
|
|
|
|
|
class BasicRegister:
|
2023-06-26 21:58:24 +03:00
|
|
|
"""
|
|
|
|
The BasicRegister represents a hardware register capable of manipulating multiple bits at a time.
|
2023-06-26 00:26:09 +03:00
|
|
|
|
|
|
|
:param deque[bool] memory: The bits stored inside the register.
|
|
|
|
"""
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
def __init__(self, memory: deque[bool]):
|
|
|
|
self.memory: deque[bool] = memory
|
2023-06-26 00:26:09 +03:00
|
|
|
|
2023-06-27 14:07:47 +03:00
|
|
|
def __repr__(self) -> str:
|
2023-06-28 12:36:02 +03:00
|
|
|
return "".join([str(int(value)) for value in self.memory])
|
2023-06-27 14:07:47 +03:00
|
|
|
|
2023-06-26 00:26:09 +03:00
|
|
|
def __str__(self) -> str:
|
2023-06-28 12:36:02 +03:00
|
|
|
return "".join([str(int(value)) for value in self.memory])
|
2023-06-26 00:26:09 +03:00
|
|
|
|
2023-06-27 14:07:47 +03:00
|
|
|
def __len__(self) -> int:
|
|
|
|
return len(self.memory)
|
|
|
|
|
2023-06-26 21:58:24 +03:00
|
|
|
def adjusted_by_size(self, resulting_size: int) -> Self:
|
|
|
|
"""
|
|
|
|
Adjusts a register to a given size.
|
|
|
|
|
|
|
|
:param int resulting_size: The size of the resulting register.
|
|
|
|
|
|
|
|
:return: A register of a specified size.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
current_memory_size: int = len(self.memory)
|
|
|
|
return BasicRegister(
|
2023-06-28 14:49:35 +03:00
|
|
|
deque([False] * max(resulting_size - current_memory_size, 0) + list(self.memory)[-resulting_size:])
|
2023-06-26 21:58:24 +03:00
|
|
|
)
|
|
|
|
|
2023-06-27 22:47:13 +03:00
|
|
|
def negate(self):
|
2023-06-27 17:49:33 +03:00
|
|
|
"""
|
2023-06-28 14:49:35 +03:00
|
|
|
Performs logical negation on the register.
|
2023-06-27 17:49:33 +03:00
|
|
|
"""
|
2023-06-26 00:26:09 +03:00
|
|
|
self.memory = deque([not value for value in self.memory])
|
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
def left_shift(self, shift_in_value: bool = False, bits_shifted: int = 1) -> deque[bool]:
|
|
|
|
"""
|
2023-06-28 14:49:35 +03:00
|
|
|
Shifts the register to the left by a specified number of steps.
|
2023-06-27 17:49:33 +03:00
|
|
|
|
|
|
|
:param bool shift_in_value: The value that shifts inside the freed space.
|
|
|
|
:param int bits_shifted: The number of bits by which the register is shifted.
|
|
|
|
|
|
|
|
:return: The bits shifted outside the register.
|
|
|
|
:rtype: deque[bool]
|
|
|
|
"""
|
|
|
|
self.memory.extend([shift_in_value] * bits_shifted)
|
|
|
|
shifted_bits: deque[bool] = deque([self.memory.popleft() for _i in range(bits_shifted)])
|
|
|
|
return shifted_bits
|
|
|
|
|
|
|
|
def right_shift(self, shift_in_value: bool = False, bits_shifted: int = 1) -> deque[bool]:
|
|
|
|
"""
|
|
|
|
Shifts the register to the right by a specified number of steps
|
|
|
|
|
|
|
|
:param bool shift_in_value: The value that shifts inside the freed space.
|
|
|
|
:param int bits_shifted: The number of bits by which the register is shifted.
|
2023-06-26 00:26:09 +03:00
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
:return: The bits shifted outside the register.
|
|
|
|
:rtype: deque[bool]
|
|
|
|
"""
|
|
|
|
self.memory.extendleft([shift_in_value] * bits_shifted)
|
|
|
|
shifted_bits: deque[bool] = deque([self.memory.pop() for _i in range(bits_shifted)])
|
|
|
|
return shifted_bits
|
2023-06-26 00:26:09 +03:00
|
|
|
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
class Counter(BasicRegister):
|
2023-06-27 22:00:15 +03:00
|
|
|
"""
|
|
|
|
The Counter represents a hardware register specifically designed for countdowns.
|
|
|
|
|
|
|
|
:param int value: Initial numeric value this Counter holds.
|
|
|
|
"""
|
|
|
|
|
|
|
|
def __init__(self, value: int):
|
2023-06-28 14:49:35 +03:00
|
|
|
# memory: deque[bool] = deque([i == "1" for i in bin(value)[2:]])
|
|
|
|
super().__init__(deque([i == "1" for i in bin(value)[2:]]))
|
|
|
|
# self.memory: deque[bool] = deque([i == "1" for i in bin(value)[2:]])
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
def __repr__(self) -> str:
|
2023-06-28 12:36:02 +03:00
|
|
|
return "".join([str(int(value)) for value in self.memory])
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
def __str__(self) -> str:
|
2023-06-28 12:36:02 +03:00
|
|
|
return "".join([str(int(value)) for value in self.memory])
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
def __len__(self) -> int:
|
|
|
|
return len(self.memory)
|
|
|
|
|
|
|
|
def decrement(self):
|
2023-06-28 14:49:35 +03:00
|
|
|
self.memory = binary_subtraction(self, BasicRegister(deque([False] * (len(self.memory) - 1) + [True]))).memory
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
def non_zero(self) -> bool:
|
|
|
|
return any(self.memory)
|
|
|
|
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
def get_memory(variable_name: str) -> deque[bool]:
|
2023-06-26 00:26:09 +03:00
|
|
|
"""
|
|
|
|
Reads user input to be used as a memory array.
|
|
|
|
|
|
|
|
:param str variable_name: The name to be displayed in the input line.
|
|
|
|
|
|
|
|
:return: A list of boolean values read from user.
|
|
|
|
:rtype: list[bool]
|
|
|
|
"""
|
|
|
|
while True:
|
|
|
|
input_chars: list[str] = list(input(f"Enter {variable_name}: "))
|
|
|
|
|
|
|
|
if all(character in ["0", "1"] for character in input_chars):
|
2023-06-28 14:49:35 +03:00
|
|
|
return deque([True if character == "1" else False for character in input_chars])
|
2023-06-26 00:26:09 +03:00
|
|
|
else:
|
|
|
|
print(f"[ERROR] The {variable_name} may contain only 1-s and 0-s!")
|
2023-06-26 21:05:45 +03:00
|
|
|
|
|
|
|
|
2023-06-27 17:05:40 +03:00
|
|
|
def binary_sum_with_carry(first_term: BasicRegister, second_term: BasicRegister) -> tuple[BasicRegister, int]:
|
2023-06-27 17:49:33 +03:00
|
|
|
"""
|
|
|
|
Sums two registers' values and keeps the carry-out.
|
|
|
|
|
|
|
|
:param BasicRegister first_term: First register.
|
|
|
|
:param BasicRegister second_term: Second register.
|
|
|
|
|
|
|
|
:return: Register containing the sum and the carry-out bit.
|
|
|
|
:rtype: tuple[BasicRegister, int]
|
|
|
|
"""
|
2023-06-28 14:49:35 +03:00
|
|
|
result_term = BasicRegister(deque([False] * len(first_term)))
|
2023-06-27 17:05:40 +03:00
|
|
|
|
|
|
|
carry = False
|
2023-06-27 22:09:45 +03:00
|
|
|
for i in range(len(first_term) - 1, -1, -1):
|
2023-06-27 17:05:40 +03:00
|
|
|
current_bit_sum = first_term.memory[i] + second_term.memory[i] + carry
|
|
|
|
carry = bool(current_bit_sum & 2)
|
|
|
|
result_term.memory[i] = bool(current_bit_sum & 1)
|
|
|
|
|
2023-06-27 22:09:45 +03:00
|
|
|
return result_term, carry
|
2023-06-27 17:05:40 +03:00
|
|
|
|
|
|
|
|
|
|
|
def binary_sum(first_term: BasicRegister, second_term: BasicRegister) -> BasicRegister:
|
2023-06-26 21:05:45 +03:00
|
|
|
"""
|
2023-06-27 17:49:33 +03:00
|
|
|
Sums two terms containing binary numbers.
|
2023-06-26 21:05:45 +03:00
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
:param BasicRegister first_term: First register to add.
|
|
|
|
:param BasicRegister second_term: Second register to add.
|
2023-06-26 21:05:45 +03:00
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
:return: Register containing the sum.
|
|
|
|
:rtype: BasicRegister
|
2023-06-26 21:05:45 +03:00
|
|
|
"""
|
2023-06-27 17:05:40 +03:00
|
|
|
return binary_sum_with_carry(first_term, second_term)[0]
|
2023-06-27 15:34:39 +03:00
|
|
|
|
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
def binary_subtraction(minuend: BasicRegister, subtrahend: BasicRegister) -> BasicRegister:
|
|
|
|
"""
|
|
|
|
Subtracts the second term from the first in binary using ones' complement.
|
|
|
|
|
|
|
|
:param BasicRegister minuend: Register to subtract from.
|
|
|
|
:param BasicRegister subtrahend: Register to subtract by.
|
2023-06-27 15:34:39 +03:00
|
|
|
|
2023-06-27 17:49:33 +03:00
|
|
|
:return: Register containing the difference.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
2023-07-29 18:42:06 +03:00
|
|
|
subtrahend = BasicRegister(subtrahend.memory)
|
2023-06-27 22:47:13 +03:00
|
|
|
subtrahend.negate()
|
2023-06-27 17:49:33 +03:00
|
|
|
|
|
|
|
difference: BasicRegister
|
2023-06-27 15:53:20 +03:00
|
|
|
final_carry: bool
|
2023-06-27 17:49:33 +03:00
|
|
|
difference, final_carry = binary_sum_with_carry(minuend, subtrahend)
|
2023-06-27 15:34:39 +03:00
|
|
|
|
2023-06-27 15:53:20 +03:00
|
|
|
if final_carry:
|
2023-06-28 14:49:35 +03:00
|
|
|
return binary_sum(difference, BasicRegister(deque([False] * (len(difference) - 1) + [True])))
|
2023-06-27 15:53:20 +03:00
|
|
|
else:
|
2023-06-27 22:47:13 +03:00
|
|
|
difference.negate()
|
2023-06-27 17:49:33 +03:00
|
|
|
return difference
|
|
|
|
|
|
|
|
|
2023-07-29 18:42:06 +03:00
|
|
|
def binary_subtraction_second_complement(minuend: BasicRegister, subtrahend: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, bool]:
|
|
|
|
"""
|
|
|
|
Subtracts the second term from the first in binary using seconds' complement.
|
|
|
|
|
|
|
|
:param BasicRegister minuend: Register to subtract from.
|
|
|
|
:param BasicRegister subtrahend: Register to subtract by.
|
|
|
|
|
|
|
|
:return: Register containing the difference.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
subtrahend = BasicRegister(subtrahend.memory)
|
|
|
|
subtrahend.negate()
|
|
|
|
|
|
|
|
subtrahend = binary_sum(*align_registers(subtrahend, BasicRegister([True])))
|
|
|
|
|
|
|
|
difference: BasicRegister
|
|
|
|
final_carry: bool
|
|
|
|
difference, final_carry = binary_sum_with_carry(minuend, subtrahend)
|
|
|
|
|
|
|
|
return difference, final_carry
|
|
|
|
|
|
|
|
|
2023-06-27 17:53:18 +03:00
|
|
|
def align_registers(*registers: BasicRegister) -> tuple[BasicRegister, ...]:
|
2023-06-27 17:49:03 +03:00
|
|
|
"""
|
|
|
|
Aligns registers by the length of the bigger one.
|
2023-06-27 15:34:39 +03:00
|
|
|
|
2023-06-27 17:53:18 +03:00
|
|
|
:param BasicRegister registers: Registers to align.
|
2023-06-27 17:49:03 +03:00
|
|
|
|
|
|
|
:return: Aligned registers.
|
|
|
|
:rtype: tuple[BasicRegister, ...]
|
|
|
|
"""
|
2023-06-27 17:53:18 +03:00
|
|
|
required_size: int = max(map(len, registers))
|
|
|
|
return tuple(reg.adjusted_by_size(required_size) for reg in registers)
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
def format_device_state_table(table) -> str:
|
|
|
|
pt = PrettyTable()
|
|
|
|
pt.field_names = table[0]
|
|
|
|
|
|
|
|
for block in table[1:]:
|
|
|
|
for line in block[:-1]:
|
|
|
|
pt.add_row(line)
|
2023-06-28 14:49:35 +03:00
|
|
|
pt.add_row(block[-1], divider=True)
|
2023-06-28 12:36:02 +03:00
|
|
|
|
|
|
|
return pt.get_string()
|
|
|
|
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
def binary_multiplication_method_1(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
2023-06-27 22:00:15 +03:00
|
|
|
"""
|
|
|
|
Multiplies two terms containing binary numbers using first method.
|
|
|
|
|
|
|
|
:param BasicRegister first_term: First register to multiply.
|
|
|
|
:param BasicRegister second_term: Second register to multiply.
|
|
|
|
|
|
|
|
:return: Register containing the product.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
rg1 = BasicRegister(deque([False] * n))
|
2023-06-27 22:00:15 +03:00
|
|
|
rg2 = BasicRegister(first_term.memory)
|
|
|
|
rg3 = BasicRegister(second_term.memory)
|
|
|
|
ct = Counter(n)
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table = [["iter", "RG1", "RG2", "RG3", "CT", "MicroOperations"]]
|
|
|
|
|
|
|
|
i = 0
|
|
|
|
data_table.append([])
|
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, ct, "-"])))
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
while ct.non_zero():
|
2023-06-28 12:36:02 +03:00
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
if rg2.memory[n-1]:
|
|
|
|
rg1 = binary_sum(rg1, rg3)
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, ct, "RG1 := RG1 + RG3"])))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
rg2.right_shift(rg1.memory[n-1])
|
|
|
|
rg1.right_shift()
|
|
|
|
ct.decrement()
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, ct, "RG2 := RG1[1].r(RG2)\nRG1 := 0.r(RG1)\nCT := CT - 1"])))
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
return BasicRegister(rg1.memory + rg2.memory), data_table
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
def binary_multiplication_method_2(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
2023-06-27 22:00:15 +03:00
|
|
|
"""
|
|
|
|
Multiplies two terms containing binary numbers using second method.
|
|
|
|
|
|
|
|
:param BasicRegister first_term: First register to multiply.
|
|
|
|
:param BasicRegister second_term: Second register to multiply.
|
|
|
|
|
|
|
|
:return: Register containing the product.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
rg1 = BasicRegister(deque([False] * (2*n)))
|
2023-06-27 22:00:15 +03:00
|
|
|
rg2 = BasicRegister(first_term.memory)
|
2023-06-28 14:49:35 +03:00
|
|
|
rg3 = BasicRegister(deque([False] * n + list(second_term.memory)))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
i = 0
|
2023-06-28 14:49:35 +03:00
|
|
|
data_table = [["iter", "RG1", "RG2", "RG3", "MicroOperations"], []]
|
2023-06-28 12:36:02 +03:00
|
|
|
|
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "-"])))
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
while any(rg2.memory):
|
2023-06-28 12:36:02 +03:00
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
if rg2.memory[n-1]:
|
|
|
|
rg1 = binary_sum(rg1, rg3)
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "RG1 := RG1 + RG3"])))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
rg2.right_shift()
|
|
|
|
rg3.left_shift()
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "RG2 := 0.r(RG2)\nRG3 := l(RG3).0"])))
|
|
|
|
|
|
|
|
return rg1, data_table
|
2023-06-27 22:00:15 +03:00
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
|
|
|
|
def binary_multiplication_method_3(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
2023-06-27 22:00:15 +03:00
|
|
|
"""
|
|
|
|
Multiplies two terms containing binary numbers using third method.
|
|
|
|
|
|
|
|
:param BasicRegister first_term: First register to multiply.
|
|
|
|
:param BasicRegister second_term: Second register to multiply.
|
|
|
|
|
|
|
|
:return: Register containing the product.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table = [["iter", "RG2", "RG1", "RG3", "CT", "MicroOperations"]]
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
rg1 = BasicRegister(deque([False] * n))
|
|
|
|
rg2 = BasicRegister(first_term.memory + deque([False]))
|
|
|
|
rg3 = BasicRegister(deque([False] * (n+1)) + second_term.memory)
|
2023-06-27 22:00:15 +03:00
|
|
|
ct = Counter(n)
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
i = 0
|
|
|
|
data_table.append([])
|
|
|
|
data_table[-1].append(list(map(str, [i, rg2, rg1, rg3, ct, "-"])))
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
while ct.non_zero():
|
2023-06-28 12:36:02 +03:00
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
if rg2.memory[0]:
|
|
|
|
result: list[bool] = list(binary_sum(BasicRegister(rg2.memory + rg1.memory), rg3).memory)
|
2023-06-28 14:49:35 +03:00
|
|
|
rg2 = BasicRegister(deque(result[:n+1]))
|
|
|
|
rg1 = BasicRegister(deque(result[n+1:]))
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg2, rg1, rg3, ct, "RG2.RG1 := RG2.RG1 + RG3"])))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
rg2.left_shift(rg1.memory[0])
|
|
|
|
rg1.left_shift()
|
|
|
|
ct.decrement()
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg2, rg1, rg3, ct, "RG2.RG1 := l(RG2.RG1).0\nCT := CT - 1"])))
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
return BasicRegister(deque(list(rg2.memory + rg1.memory)[:-1])), data_table
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
def binary_multiplication_method_4(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
2023-06-27 22:00:15 +03:00
|
|
|
"""
|
|
|
|
Multiplies two terms containing binary numbers using fourth method.
|
|
|
|
|
|
|
|
:param BasicRegister first_term: First register to multiply.
|
|
|
|
:param BasicRegister second_term: Second register to multiply.
|
|
|
|
|
|
|
|
:return: Register containing the product.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
rg1 = BasicRegister(deque([False] * (2*n+1)))
|
2023-06-27 22:00:15 +03:00
|
|
|
rg2 = BasicRegister(first_term.memory)
|
2023-06-28 14:49:35 +03:00
|
|
|
rg3 = BasicRegister(deque([False]) + second_term.memory + deque([False] * n))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table = [["iter", "RG1", "RG2", "RG3", "MicroOperations"]]
|
|
|
|
|
|
|
|
i = 0
|
|
|
|
data_table.append([])
|
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "-"])))
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
while any(rg2.memory):
|
2023-06-28 12:36:02 +03:00
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
2023-06-27 22:00:15 +03:00
|
|
|
if rg2.memory[0]:
|
|
|
|
rg1 = binary_sum(rg1, rg3)
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "RG1 := RG1 + RG3"])))
|
2023-06-27 22:00:15 +03:00
|
|
|
|
|
|
|
rg2.left_shift()
|
|
|
|
rg3.right_shift()
|
|
|
|
|
2023-06-28 12:36:02 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg1, rg2, rg3, "RG2 := l(RG2).0\nRG3 := 0.r(RG3)"])))
|
|
|
|
|
2023-06-28 14:49:35 +03:00
|
|
|
return BasicRegister(deque(list(rg1.memory)[:-1])), data_table
|
2023-07-29 18:42:06 +03:00
|
|
|
|
|
|
|
def binary_division_method_1(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
|
|
|
"""
|
|
|
|
Divides first term by the second term containing binary numbers using first method.
|
|
|
|
|
|
|
|
:param: BasicRegister first_term: Register being divided.
|
|
|
|
:param: BasicRegister second_term: Register being divided by.
|
|
|
|
|
|
|
|
:return: Register containing the division result.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
|
|
|
rg1 = BasicRegister(deque([False, False]) + second_term.memory)
|
|
|
|
rg2 = BasicRegister(deque([False, False]) + first_term.memory)
|
|
|
|
rg3 = BasicRegister(deque([True] * (n+1)))
|
|
|
|
|
|
|
|
data_table = [["iter", "RG3", "RG2", "RG1", "MicroOperations"]]
|
|
|
|
i = 0
|
|
|
|
|
|
|
|
data_table.append([])
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "-"])))
|
|
|
|
|
|
|
|
while rg3.memory[0]:
|
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
|
|
|
if rg2.memory[0]:
|
|
|
|
rg2 = binary_sum(rg2, rg1)
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "RG2 := RG2 + RG1"])))
|
|
|
|
else:
|
|
|
|
rg2, _ = binary_subtraction_second_complement(rg2, rg1)
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "RG2 := RG2 - RG1"])))
|
|
|
|
|
2023-07-29 20:50:40 +03:00
|
|
|
rg3.left_shift(not rg2.memory[0])
|
2023-07-29 18:42:06 +03:00
|
|
|
rg2.left_shift()
|
2023-07-29 20:50:40 +03:00
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, f"RG3 := l(RG3).!RG2[{n+2}]\nRG2 := l(RG2).0"])))
|
2023-07-29 18:42:06 +03:00
|
|
|
|
|
|
|
return BasicRegister(deque(list(rg3.memory)[1:])), data_table
|
|
|
|
|
|
|
|
def binary_division_method_2(first_term: BasicRegister, second_term: BasicRegister) \
|
|
|
|
-> tuple[BasicRegister, list[list[str]]]:
|
|
|
|
"""
|
|
|
|
Divides first term by the second term containing binary numbers using second method.
|
|
|
|
|
|
|
|
:param: BasicRegister first_term: Register being divided.
|
|
|
|
:param: BasicRegister second_term: Register being divided by.
|
|
|
|
|
|
|
|
:return: Register containing the division result.
|
|
|
|
:rtype: BasicRegister
|
|
|
|
"""
|
|
|
|
|
|
|
|
first_term, second_term = align_registers(first_term, second_term)
|
|
|
|
n: int = len(first_term)
|
|
|
|
|
|
|
|
rg1 = BasicRegister(deque([False]) + second_term.memory + deque([False]*n))
|
|
|
|
rg2 = BasicRegister(deque([False]) + first_term.memory + deque([False]*n))
|
|
|
|
rg3 = BasicRegister(deque([True] * (n+1)))
|
|
|
|
|
|
|
|
data_table = [["iter", "RG3", "RG2", "RG1", "MicroOperations"]]
|
|
|
|
i = 0
|
|
|
|
carry = False
|
|
|
|
|
|
|
|
data_table.append([])
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "-"])))
|
|
|
|
|
|
|
|
while rg3.memory[0]:
|
|
|
|
i += 1
|
|
|
|
data_table.append([])
|
|
|
|
|
|
|
|
if rg2.memory[0]:
|
|
|
|
rg2, carry = binary_sum_with_carry(rg2, rg1)
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "RG2 := RG2 + RG1"])))
|
|
|
|
else:
|
|
|
|
rg2, carry = binary_subtraction_second_complement(rg2, rg1)
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, "RG2 := RG2 - RG1"])))
|
|
|
|
|
|
|
|
rg3.left_shift(carry)
|
|
|
|
rg1.right_shift()
|
|
|
|
data_table[-1].append(list(map(str, [i, rg3, rg2, rg1, f"RG3 := l(RG3).SM[p]\nRG1 := 0.r(RG1)"])))
|
|
|
|
|
|
|
|
return BasicRegister(deque(list(rg3.memory)[1:])), data_table
|